1. Technical Field
The present invention relates to a method for manufacturing a nitride semiconductor device, such as a light emitting element or an electronic device that uses a group III nitride semiconductor having a p-type conductivity.
2. Background Art
A group III nitride semiconductor is primarily a gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), or a mixed crystal of these.
This nitride semiconductor is used in light emitting diodes (LED), laser diodes (LD), and other light emitting devices, as well as in Schottky barrier diodes (SBD), field effect transistors (FET), and other electronic devices for power device applications.
n-type and p-type conductivity control is possible with these types of nitride semiconductors when using silicon (Si) or magnesium (Mg) as a dopant. Specifically, a desired emission can be obtained by forming a pn junction in a light emitting device and implanting electrons and holes in a quantum well layer for recombination. For these types of light emitting devices, it is desired to realize low resistance ohmic contact and to realize a high hole concentration (p+ layer) for performance improvement, namely, a reduction of forward resistance.
Further, for electronic devices, FETs using an AlGaN/GaN heterostructure (AlGaN/GaN-HFET) utilize a two-dimensional electron gas of high concentration generated at the AlGaN/GaN interface to realize a semiconductor element with low on-resistance. A method to realize high withstand voltage in these types of electronic devices by arranging a body electrode in a p+ layer by forming the p+ layer in the element is known (Japanese Unexamined Patent Application Publication No. 2010-232279A). That is, withstand voltage can be improved by removing, from the body electrode, the hole from the electron hole pair generated by an avalanche phenomenon that occurs when the drain voltage is high.
However, there are concerns about safety when a malfunction occurs in the power supply circuit due to the normally-on characteristic in the AlGaN/GaN-HFET described above. When considering a failsafe, normally-off is desired in the semiconductor element.
Known examples of normally-off methods include arranging p-type GaN under the gate electrode in a GaN based MOSFET (Japanese Unexamined Patent Application Publication No. 2008-311392A and Japanese Unexamined Patent Application Publication No. 2009-246292A) or in an AlGaN/GaN-HFET structure (Japanese Patent No. 4755961B).
In a group III nitride semiconductor, Mg functions as an acceptor by substituting in the group III site. When forming a p-type GaN layer using a metal organic chemical vapor deposition (MOCVD) method, Mg can introduce biscyclopentadienylmagnesium (Cp2 Mg) as a source gas. In this case, because Mg forms a compound with hydrogen (Mg—H), the activation rate as an acceptor decreases.
Further, the acceptor level produced by Mg in the GaN layer (Ga substitute; MgGa) is positioned at about 170 meV from the valence band so an ionization rate of only a few percent can be expected at room temperature. Mg—H can be broken down after crystal growth by heat treatment and/or irradiating with a thermal neutron beam (Japanese Patent No 4124156B). However, the ionization rate is a physically determined amount and there is no room for artificial improvements. Accordingly, in order to obtain a high hole concentration of approximately 1018 to 1019 cm−3, Mg doping that exceeds 1020 to 1021 cm−3 is required.
For this, with the conventional technique, Mg is doped independently during crystal growth of GaN. Therefore, Mg doping is limited after Ga site substitution from approximately the latter half of 1019 cm−3 to the first half of 1020 cm−3. This is because the Mg, when doping in high concentration, either enters an interstitial site or forms a nitrogen vacancy (VN) due to a self-compensation effect exhibited by n-type conductivity. Mg that has entered an interstitial site adversely affects electrical characteristics due to segregation in low angle grain boundaries and threading dislocation in the crystal and on the surface.
Further, it is known that when Mg is segregated into GaN bulk, an anti-phase boundary is formed causing polarity to reverse (D. S. Green, E. Haus, F. Wu, L. Chen, U. K. Mishra, and J. S. Speck, Journal of Vacuum Science & Technology B 2003, vol. 21, pg. 1804). When polarity is reversed, the crystal quality of the GaN layer epitaxially grown further above that region is significantly lower. Moreover, because Ga interstitial atoms are also formed in addition to nitrogen vacancy (VN), there are problems that bring about a current collapse phenomenon and characteristic fluctuation in the electronic device. Therefore, realizing a p-type GaN layer that provides the quality required by an electronic device has been difficult in a GaN based electronic device.
In response to this, a technique for simultaneously doping Si and oxygen (O), which is an n-type dopant, has been proposed as a method for introducing a high concentration of Mg (Japanese Patent No. 3223295B). According to the technique described in Japanese Patent No. 3223295B, doping with an n-type dopant and a p-type dopant in a ratio of 1:2 forms an Si—Mg2 pair in GaN to effectively function as an acceptor.
However, formation control of this type of donor-acceptor pair is difficult, and the above method has a problem in that an n-type dopant present alone may be introduced. When an n-type dopant remains, hole concentration is reduced. Further, the Si—Mg2 pair is formed not only at the low acceptor level but also at a deep level. Furthermore, because the deep level introduces the current collapse phenomenon, it is not suitable for electronic device applications.
Additionally, similar to the technique described in Japanese Patent No. 3223295B, there is a report where high hole concentrations have been realized by simultaneously doping an n-type dopant and a p-type dopant (Japanese Patent No. 3322179B). Japanese Patent No. 3322179B describes that simultaneously doping Mg with an n-type dopant relaxes distortion around Mg so that Mg does not enter an interstitial site and promotes the formation of MgGa. However, in order to obtain a hole concentration of 1019 cm−3, an n-type dopant (Si) must be introduced in a range of 1/10 to ½ of Mg. Because this n-type dopant remains in GaN, it has a problem in that the element characteristics fluctuate due to external disturbances such as electrification.
Further, in contrast to Japanese Patent No. 3223295B and Japanese Patent No. 3322179B, testing has been conducted to try to improve hole concentration by simultaneously doping two types of p-type dopants (Japanese Patent No. 3461112B). Japanese Patent No. 3461112B describes that simultaneously doping Zn that forms an acceptor level deeper than Mg increases hole concentration as a result of compensating for n-type residual carriers. However, because 1018 cm−3 or more of Zn remains in the GaN with this method, the problem of bringing about the current collapse phenomenon in the electronic device remains.
Concerning the request for a normally-off AlGaN/GaN-HFET, a technique that forms a p-type GaN layer on AlGaN is known as described in Japanese Patent No. 4755961B. However, in order to obtain desired characteristics in the AlGaN/GaN-HFET, the acceptor amount must be increased such that the layer thickness of the p-type GaN layer must be at least 15 nm. On account of this, there is a problem in that leakage current increases through the p-type GaN layer.
In light of the above, an object of the present invention is to provide a method for manufacturing a nitride semiconductor device that can effectively dope magnesium of a p-type dopant and that can realize a high acceptor concentration and a high hole concentration in a group III nitride semiconductor.